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1 tm file number 3214.5 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright ?intersil corporation 2001 HI5812 cmos 20 microsecond, 12-bit, sampling a/d converter with internal track and hold the HI5812 is a fast, low power, 12-bit, successive approximation analog-to-digital converter. it can operate from a single 3v to 6v supply and typically draws just 1.9ma when operating at 5v. the HI5812 features a built-in track and hold. the conversion time is as low as 20 s with a 5v supply. the twelve data outputs feature full high speed cmos three-state bus driver capability, and are latched and held through a full conversion cycle. the output is user selectable, i.e., 12-bit, 8-bit (msbs), and/or 4-bit (lsbs). a data ready ?g, and conversion-start input complete the digital interface. an internal clock is provided and is available as an output. the clock may also be over-driven by an external source. features conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 s throughput rate . . . . . . . . . . . . . . . . . . . . . . . . 50 ksps built-in track and hold guaranteed no missing codes over temperature single supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . +5v maximum power consumption. . . . . . . . . . . . . . . . 25mw internal or external clock applications remote low power data acquisition systems digital audio dsp modems general purpose dsp front end p controlled measurement system professional audio positioner/fader pinout HI5812 (pdip, soic) top view ordering information part number inl (lsb) (max over temp.) temp. range ( o c) package pkg. no. HI5812jip 1.5 -40 to 85 24 ld pdip e24.3 HI5812jib 1.5 -40 to 85 24 ld soic m24.3 HI5812kib 1.0 -40 to 85 24 ld soic m24.3 1 2 3 4 5 6 7 8 9 10 11 12 drdy (lsb) d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 v ss 16 17 18 19 20 21 22 23 24 15 14 13 v dd clk str t v ref - v ref + v aa + oem d11 (msb) d10 oel v in v aa - data sheet january 2001
2 functional block diagram 12-bit successive approximation register clock to internal logic v dd v ss v in v ref + v aa + v aa - v ref - 64c 63 p1 50 ? substrate 16c 32c 8c 4c 2c c 16c 32c 8c 4c 2c c c clk drdy oem d11 (msb) d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) oel str t 12-bit edge triggered ??latches control + timing HI5812
3 absolute maximum ratings thermal information supply voltage v dd to v ss . . . . . . . . . . . . . . . . . . . . (v ss -0.5v) < v dd < +6.5v v aa + to v aa - . . . . . . . . . . . . . . . . . . . (v ss -0.5v) to (v ss +6.5v) v aa + to v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3v analog and reference inputs v in , v ref +, v ref - . . . . . . . . (v ss -0.3v) < v ina < (v dd +0.3v) digital i/o pins . . . . . . . . . . . . . . . (v ss -0.3v) < v i/o < (v dd +0.3v) operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 1) ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 maximum junction temperature plastic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -65 c to 150 o c maximum lead temperature (soldering, 10s). . . . . . . . . . . . .300 o c (soic - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. ja is measured with the component mounted on a low effective thermal conductivity test board in free air. see tech brief tb379 fo r details. electrical speci?ations v dd = v aa + = 5v, v ref + = +4.608v, v ss = v aa - = v ref - = gnd, clk = external 750khz, unless otherwise speci?d parameter test conditions 25 o c - 40 o c to 85 o c units min typ max min max accuracy resolution 12 - - 12 - bits integral linearity error, inl (end point) j-- 1.5 - 1.5 lsb k-- 1.0 - 1.0 lsb differential linearity error, dnl j - - 2.0 - 2.0 lsb k-- 1.0 - 1.0 lsb gain error, fse (adjustable to zero) j-- 3.0 - 3.0 lsb k-- 2.5 - 2.5 lsb offset error, v os (adjustable to zero) j-- 2.0 - 2.0 lsb k-- 1.0 - 1.0 lsb power supply rejection, psrr offset error psrr gain error psrr v ref = 4v v dd = v aa + = 5v 5% v dd = v aa + = 5v 5% - 0.1 0.1 0.5 0.5 - 0.5 0.5 lsb lsb dynamic characteristics signal to noise ratio, sinad rms signal rms noise + distortion jf s = internal clock, f in = 1khz f s = 750khz, f in = 1khz - 68.8 69.2 -- -db db kf s = internal clock, f in = 1khz f s = 750khz, f in = 1khz - 71.0 71.5 -- -db db signal to noise ratio, snr rms signal rms noise jf s = internal clock, f in = 1khz f s = 750khz, f in = 1khz - 70.5 71.1 -- -db db kf s = internal clock, f in = 1khz f s = 750khz, f in = 1khz - 71.5 72.1 -- -db db total harmonic distortion, thd j f s = internal clock, f in = 1khz f s = 750khz, f in = 1khz - -73.9 -73.8 - - - dbc dbc kf s = internal clock, f in = 1khz f s = 750khz, f in = 1khz - -80.3 -79.0 - - - dbc dbc spurious free dynamic range, sfdr jf s =internal clock, f in = 1khz f s = 750khz, f in = 1khz - -75.4 -75.1 -- -db db kf s = internal clock, f in = 1khz f s = 750khz, f in = 1khz - -80.9 -79.6 -- -db db HI5812
4 analog input input current, dynamic at v in = v ref +, 0v - 50 100 - 100 a input current, static conversion stopped - 0.4 10 - 10 a input bandwidth -3db - 1 - - - mhz reference input current - 160 - - - a input series resistance, r s in series with input c sample - 420 - - - w input capacitance, c sample during sample state - 380 - - - pf input capacitance, c hold during hold state - 20 - - - pf digital inputs oel, oem, str t high-level input voltage, v ih 2.4 - - 2.4 - v low-level input voltage, v il - - 0.8 - 0.8 v input leakage current, i il except clk, v in = 0v, 5v - - 10 - 10 a input capacitance, c in -10- - - pf digital outputs high-level output voltage, v oh i source = -400 a 4.6 - - 4.6 - v low-level output voltage, v ol i sink = 1.6ma - - 0.4 - 0.4 v three-state leakage, i oz except drdy, v out = 0v, 5v - - 10 - 10 a output capacitance, c out except drdy - 20 - - - pf clock high-level output voltage, v oh i source = -100 a (note 2) 4 - - 4 - v low-level output voltage, v ol i sink = 100 a (note 2) - - 1 - 1 v input current clk only, v in = 0v, 5v - - 5- 5ma timing conversion time (t conv + t acq ) (includes acquisition time) 20 - - 20 - s clock frequency internal clock, (clk = open) 200 300 400 150 500 khz external clk (note 2) 0.05 2 1.5 0.05 1.5 mhz clock pulse width, t low , t high external clk (note 2) 100 - - 100 - ns aperture delay, t d apr (note 2) - 35 50 - 70 ns clock to data ready delay, t d1 drdy (note 2) - 105 150 - 180 ns clock to data ready delay, t d2 drdy (note 2) - 100 160 - 195 ns start removal time, t r str t (note 2) 75 30 - 75 - ns start setup time, t su strt (note 2) 85 60 - 100 - ns start pulse width, t w strt (note 2) 10 4 - 15 - ns start to data ready delay, t d3 drdy (note 2) - 65 105 - 120 ns clock delay from start, t d strt (note 2) - 60 - - - ns output enable delay, t en (note 2) - 20 30 - 50 ns output disabled delay, t dis (note 2) - 80 95 - 120 ns electrical speci?ations v dd = v aa + = 5v, v ref + = +4.608v, v ss = v aa - = v ref - = gnd, clk = external 750khz, unless otherwise speci?d (continued) parameter test conditions 25 o c - 40 o c to 85 o c units min typ max min max HI5812
5 power supply characteristics supply current, i dd + i aa - 1.9 5 - 8 ma note: 2. parameter guaranteed by design or characterization, not production tested. timing diagrams figure 1. continuous conversion mode figure 2. single shot mode external clock electrical speci?ations v dd = v aa + = 5v, v ref + = +4.608v, v ss = v aa - = v ref - = gnd, clk = external 750khz, unless otherwise speci?d (continued) parameter test conditions 25 o c - 40 o c to 85 o c units min typ max min max d0 - d11 clk (external t d2 drdy t low t high 1 2 3 4 5 - 14 15 1 2 3 str t or internal) hold n track n track n + 1 v in oel = oem = v ss drdy t d1 drdy data n - 1 data n str t hold track hold clk (external) drdy v in t r str t t su str t t w str t 15 1 2 2 2 3 4 5 t d3 drdy HI5812
6 figure 3. single shot mode internal clock figure 4a. figure 4b. figure 4. output enable/disable timing diagram figure 5. general timing load circuit timing diagrams (continued) hold track hold t r str t t d str t t w str t 15 1 2 3 4 5 t d3 drdy don? care drdy clk (internal) v in str t oel or oem d0 - d3 or d4 - d11 high t dis t en 50% 50% 10% 90% to low to pin output impedance high impedance to high -1.6ma 1.6ma 50pf +2.1v -400 a 1.6ma 50pf +2.1v HI5812
7 typical performance curves figure 6. inl vs temperature figure 7. offset voltage vs temperature figure 8. dnl vs temperature figure 9. accuracy vs reference voltage figure 10. full scale error vs temperature figure 11. power supply rejection vs temperature -60 -40 -20 0 20 40 60 80 100 120 140 1.0 0.75 0.5 0.25 0 inl error (lsbs) temperature ( o c) v dd = v aa + = 5v, v ref + = 4.608v c b a a. clk = internal b. clk = 750khz c. clk = 1mhz -60 -40 -20 0 20 40 60 80 100 120 140 1.5 0.5 1 0 temperature ( o c) v dd = v aa + = 5v b a v os error (lsbs) c a. clk = internal b. clk = 750khz c. clk = 1mhz v ref + = 4.608v -60 - 40 -20 0 20 40 60 80 100 120 140 1.0 0.75 0.5 0.25 0 temperature ( o c) v dd = v aa + = 5v, v ref + = 4.608v c b a a. clk = internal b. clk = 750khz c. clk = 1mhz dnl error (lsbs) 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 2 1.5 1 0.5 0 reference voltage, v ref (v) v dd = v aa + = 5v, t a = 25 o c fse dnl inl clk = 750khz error (lsbs) v os -60 -40 -20 0 20 40 60 80 100 120 140 2 1.5 1 0.5 0 temperature ( o c) v dd = v aa + = 5v, c a b a. clk = internal b. clk = 750khz c. clk = 1mhz fs error (lsbs) v ref + = 4.608v -60 -40 -20 0 20 40 60 80 100 120 140 0.5 0.375 0.25 0.125 0 temperature ( o c) v dd = v aa + = 5v 5% psrr fse clk = 750khz psrr v os v ref + = 4.0v psrr (lsbs) HI5812
8 figure 12. supply current vs temperature figure 13. fft spectrum figure 14. internal clock frequency vs temperature figure 15. effective bits vs input frequency figure 16. total harmonic distortion vs input frequency figure 17. signal noise ratio vs input frequency typical performance curves (continued) -60 -40 -20 0 20 40 60 80 100 120 140 8 6 3 0 temperature ( o c) supply current, i dd (ma) 7 5 4 2 1 v dd = v aa + = 5v, v ref + = 4.608v internal clock 0 500 1000 1500 amplitude (db) 0.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100.0 -110.0 -120.0 -130.0 frequency bins -10.0 2000 input frequency = 1khz sampling rate = 50khz snr = 72.1db thd = -79.1dbc peak noise = -80.9db sfdr = -80.9db sinad = 71.4db effective bits = 11.5 -140.0 -60 -40 -20 0 20 40 60 80 100 120 140 500 400 250 temperature ( o c) 450 350 300 200 150 v dd = v aa + = 5v, v ref + = 4.608v internal clock frequency (khz) input frequency (khz) 0.1 1 10 100 12 7 8 b a. clk = internal b. clk = 750khz c. clk = 1mhz v dd = v aa + = 5v v ref + = 4.608v t a = 25 o c 11 9 10 enob (bits) a c input frequency (khz) 0.1 1 10 100 -80 -50 -70 -60 b c a. clk =internal b. clk = 750khz c. clk = 1mhz v dd = v aa + = 5v v ref + = 4.608v t a = 25 o c thd (dbc) a input frequency (khz) 0.1 1 10 100 a. clk = internal b. clk = 750khz c. clk = 1mhz v dd = v aa + = 5v v ref + = 4.608v t a = 25 o c 75 50 55 70 60 65 snr (dbc) a c b HI5812
9 theory of operation HI5812 is a cmos 12-bit analog-to-digital converter that uses capacitor-charge balancing to successively approximate the analog input. a binarily weighted capacitor network forms the a/d heart of the device. see the block diagram for the HI5812. the capacitor network has a common node which is connected to a comparator. the second terminal of each capacitor is individually switchable to the input, v ref + or v ref -. during the ?st three clock periods of a conversion cycle, the switchable end of every capacitor is connected to the input and the comparator is being auto-balanced at the capacitor common node. during the fourth period, all capacitors are disconnected from the input; the one representing the msb (d11) is connected to the v ref + terminal; and the remaining capacitors to v ref -. the capacitor-common node, after the charges balance out, will indicate whether the input was above 1 / 2 of (v ref + - v ref -). at the end of the fourth period, the comparator output is stored and the msb capacitor is either left connected to v ref + (if the comparator was high) or returned to v ref -. this allows the next comparison to be at either 3 / 4 or 1 / 4 of (v ref + - v ref -). at the end of periods 5 through 14, capacitors representing d10 through d1 are tested, the result stored, and each capacitor either left at v ref + or at v ref -. at the end of the 15th period, when the lsb (d0) capacitor is tested, (d0) and all the previous results are shifted to the output registers and drivers. the capacitors are reconnected to the input, the comparator returns to the balance state, and the data-ready output goes active. the conversion cycle is now complete. analog input the analog input pin is a predominately capacitive load that changes between the track and hold periods of the conversion cycle. during hold, clock period 4 through 15, the input loading is leakage and stray capacitance, typically less than 5 a and 20pf. at the start of input tracking, clock period 1, some charge is dumped back to the input pin. the input source must have low enough impedance to dissipate the current spike by the end of the tracking period as shown in figure 18. the amount of charge is dependent on supply and input voltages. the average current is also proportional to clock frequency. as long as these current spikes settle completely by end of the signal acquisition period, converter accuracy will be preserved. the analog input is tracked for 3 clock cycles. with an external clock of 750khz the track period is 4 s. table 1. pin descriptions pin no. name description 1 drdy output ?g signifying new data is available. goes high at end of clock period 15. goes low when new conversion is started. 2 d0 bit 0 (least signi?ant bit, lsb). 3 d1 bit 1. 4 d2 bit 2. 5 d3 bit 3. 6 d4 bit 4. 7 d5 bit 5. 8 d6 bit 6. 9 d7 bit 7. 10 d8 bit 8. 11 d9 bit 9. 12 v ss digital ground (0v). 13 d10 bit 10. 14 d11 bit 11 (most signi?ant bit, msb). 15 oem three-state enable for d4-d11. active low input. 16 v aa - analog ground, (0v). 17 v aa + analog positive supply. (+5v) (see text.) 18 v in analog input. 19 v ref + reference voltage positive input, sets 4095 code end of input range. 20 v ref - reference voltage negative input, sets 0 code end of input range. 21 str t start conversion input active low, recognized after end of clock period 15. 22 clk clk input or output. conversion functions are synchronized to positive going edge. (see text.) 23 oel three-state enable for d0 d3. active low input. 24 v dd digital positive supply (+5v). 20ma 10ma 0ma 5v 0v 5v 0v i in clk drdy 200ns/div. conditions: v dd = v aa + = 5.0v, v ref + = 4.608v, v in = 4.608v, clk = 750khz, t a = 25 o c figure 18. typical analog input current HI5812
10 a simplified analog input model is presented in figure 19. during tracking, the a/d input (v in ) typically appears as a 380pf capacitor being charged through a 420 ? internal switch resistance. the time constant is 160ns. to charge this capacitor from an external ?ero ? ?source to 0.5 lsb (1/8192), the charging time must be at least 9 time constants or 1.4 s. the maximum source impedance (r source max) for a 4 s acquisition time settling to within 0.5lsb is 750 ? . if the clock frequency was slower, or the converter was not restarted immediately (causing a longer sample time), a higher source impedance could be tolerated. reference input the reference input v ref + should be driven from a low impedance source and be well decoupled. as shown in figure 20, current spikes are generated on the reference pin during each bit test of the successive approximation part of the conversion cycle as the charge- balancing capacitors are switched between v ref - and v ref + (clock periods 5 - 14). these current spikes must settle completely during each bit test of the conversion to not degrade the accuracy of the converter. therefore v ref + and v ref - should be well bypassed. reference input v ref - is normally connected directly to the analog ground plane. if v ref - is biased for nulling the converters offset it must be stable during the conversion cycle. the HI5812 is speci?d with a 4.608v reference, however, it will operate with a reference down to 3v having a slight degradation in performance. a typical graph of accuracy vs reference voltage is presented. full scale and offset adjustment in many applications the accuracy of the HI5812 would be suf?ient without any adjustments. in applications where accuracy is of utmost importance full scale and offset errors may be adjusted to zero. the v ref + and v ref - pins reference the two ends of the analog input range and may be used for offset and full scale adjustments. in a typical system the v ref - might be returned to a clean ground, and the offset adjustment done on an input ampli?r. v ref + would then be adjusted to null out the full scale error. when this is not possible, the v ref - input can be adjusted to null the offset error, however, v ref - must be well decoupled. full scale and offset error can also be adjusted to zero in the signal conditioning ampli?r driving the analog input (v in ). control signal the HI5812 may be synchronized from an external source by using the str t (start conversion) input to initiate conversion, or if str t is tied low, may be allowed to free run. each conversion cycle takes 15 clock periods. the input is tracked from clock period 1 through period 3, then disconnected as the successive approximation takes place. after the start of the next period 1 (speci?d by t d data), the output is updated. the drdy (data ready) status output goes high (speci?d by t d1 drdy) after the start of clock period 1, and returns low (speci?d by t d2 drdy) after the start of clock period 2. the 12 data bits are available in parallel on three-state bus driver outputs. when low, the oem input enables the most signi?ant byte (d4 through d11) while the oel input enables the four least signi?ant bits (d0 - d3). t en and t dis specify the output enable and disable times. if the output data is to be latched externally, either the trailing edge of data ready or the next falling edge of the clock after data ready goes high can be used. when str t input is used to initiate conversions, operation is slightly different depending on whether an internal or external clock is used. figure 3 illustrates operation with an internal clock. if the str t signal is removed (at least t r str t) before clock period 1, and is not reapplied during that period, the clock will shut off after entering period 2. the input will continue to track and the drdy output will remain high during this time. a low signal applied to str t (at least t w str t wide) can now initiate a new conversion. the str t signal (after a delay of (t d str t)) causes the clock to restart. r source v in r sw 420 ? c sample 380pf r source(max) t acq c sample in 2 n1 + () [] ------------------------------------------------------------- - r sw = figure 19. analog input model in track mode 20ma 10ma 0ma 5v 0v 5v 0v i ref+ clk drdy 2 s/div. conditions: v dd = v aa + = 5.0v, v ref + = 4.608v, v in = 2.3v, clk = 750khz, t a = 25 o c figure 20. typical reference input current HI5812
11 depending on how long the clock was shut off, the low portion of clock period 2 may be longer than during the remaining cycles. the input will continue to track until the end of period 3, the same as when free running. figure 2 illustrates the same operation as above but with an external clock. if str t is removed (at least t r str t) before clock period 2, a low signal applied to str t will drop the drdy ?g as before, and with the ?st positive-going clock edge that meets the (t su str t) setup time, the converter will continue with clock period 3. clock the HI5812 can operate either from its internal clock or from one externally supplied. the clk pin functions either as the clock output or input. all converter functions are synchronized with the rising edge of the clock signal. figure 21 shows the con?uration of the internal clock. the clock output drive is low power: if used as an output, it should not have more than 1 cmos gate load applied, and stray wiring capacitance should be kept to a minimum. the internal clock will shut down if the a/d is not restarted after a conversion. the clock could also be shut down with an open collector driver applied to the clk pin. this should only be done during the sample portion (the ?st three clock periods) of a conversion cycle, and might be useful for using the device as a digital sample and hold. if an external clock is supplied to the clk pin, it must have suf?ient drive to overcome the internal clock source. the external clock can be shut off, but again, only during the sample portion of a conversion cycle. at other times, it must be above the minimum frequency shown in the speci?ations. in the above two cases, a further restriction applies in that the clock should not be shut off during the third sample period for more than 1ms. this might cause an internal charge-pump voltage to decay. if the internal or external clock was shut off during the conversion time (clock cycles 4 through 15) of the a/d, the output might be invalid due to balancing capacitor droop. an external clock must also meet the minimum t low and t high times shown in the speci?ations. a violation may cause an internal miscount and invalidate the results. power supplies and grounding v dd and v ss are the digital supply pins: they power all internal logic and the output drivers. because the output drivers can cause fast current spikes in the v dd and v ss lines, v ss should have a low impedance path to digital ground and v dd should be well bypassed. except for v aa +, which is a substrate connection to v dd , all pins have protection diodes connected to v dd and v ss . input transients above v dd or below v ss will get steered to the digital supplies. the v aa + and v aa - terminals supply the charge-balancing comparator only. because the comparator is autobalanced between conversions, it has good low-frequency supply rejection. it does not reject well at high frequencies however; v aa - should be returned to a clean analog ground and v aa + should be rc decoupled from the digital supply as shown in figure 22. there is approximately 50 ? of substrate impedance between v dd and v aa +. this can be used, for example, as part of a low-pass rc ?ter to attenuate switching supply noise. a 10 f capacitor from v aa + to ground would attenuate 30khz noise by approximately 40db. note that back-to-back diodes should be placed from v dd to v aa + to handle supply to capacitor turn-on or turn-off current spikes. dynamic performance fast fourier transform (fft) techniques are used to evaluate the dynamic performance of the a/d. a low distortion sine wave is applied to the input of the a/d converter. the input is sampled by the a/d and its output stored in ram. the data is than transformed into the frequency domain with a 4096 point fft and analyzed to evaluate the converters dynamic performance such as snr and thd. see typical performance characteristics. signal-to-noise ratio the signal to noise ratio (snr) is the measured rms signal to rms sum of noise at a speci?d input and sampling frequency. the noise is the rms sum of all except the fundamental and the ?st ?e harmonic signals. the snr is dependent on the number of quantization levels used in the converter. the theoretical snr for an n-bit converter with no differential or integral linearity error is: snr = (6.02n + 1.76) db. for an ideal 12-bit converter the snr is 74db. differential and integral linearity errors will degrade snr. signal-to-noise + distortion ratio sinad is the measured rms signal to rms sum of noise plus harmonic power and is expressed by the following: optional clk internal 100k ? 18pf clock enable external clock figure 21. internal clock circuitry snr = 10 log sinewave signal power total noise power sinad = 10 log sinewave signal power noise + harmonic power (2nd - 6th) HI5812
12 effective number of bits the effective number of bits (enob) is derived from the sinad data; total harmonic distortion the total harmonic distortion (thd) is the ratio of the rms sum of the second through sixth harmonic components to the fundamental rms signal for a speci?d input and sampling frequency. spurious-free dynamic range the spurious-free dynamic range (sfdr) is the ratio of the fundamental rms amplitude to the rms amplitude of the next largest spur or spectral component. if the harmonics are buried in the noise ?or it is the largest peak. enob = sinad - 1.76 6.02 thd = 10 log total harmonic power (2nd - 6th harmonic) sinewave signal power sfdr = 10 log sinewave signal power highest spurious signal power table 2. code table code description input voltage ? v ref+ = 4.608v v ref- = 0.0v (v) decimal count binary output code msb lsb d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 full scale (fs) 4.6069 4095 1 1 1 1 1 1 1 1 1 1 1 1 fs - 1 lsb 4.6058 4094 1 1 1 1 1 1 1 1 1 1 1 0 3 / 4 fs 3.4560 3072 1 1 0 0 0 0 0 0 0 0 0 0 1 / 2 fs 2.3040 2048 1 0 0 0 0 0 0 0 0 0 0 0 1 / 4 fs 1.1520 1024 0 1 0 0 0 0 0 0 0 0 0 0 1 lsb 0.001125 1 0 0 0 0 0 0 0 0 0 0 0 1 zero 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? the voltages listed above represent the ideal lower transition of each output code shown as a function of the reference voltage . 0.01 f 0.1 f 10 f 4.7 f v ref+ v in v aa +v dd d11 d0 drdy oem oel str t clk 0.1 f v ref- v aa- v ss +5v output data 750khz clock 0.001 f 0.1 f 4.7 f v ref analog input . . . figure 22. ground and supply decoupling HI5812
13 die characteristics die dimensions: 3200 m x 3940 m metallization: type: alsi thickness: 11k ? 1k ? passivation: type: psg thickness: 13k ? 2.5k ? worst case current density: 1.84 x 10 5 a/cm 2 metallization mask layout HI5812 d1 d0 (lsb) drdy v dd oel clk str t v ref - v ref + v in v aa + v aa - oem v ss (msb) d9 d8 d7 d6 d5 d4 d3 d2 d11 d10 HI5812
14 HI5812 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?o series symbol list in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 1 2 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e24.3 (jedec ms-001-af issue d) 24 lead narrow body dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8 c 0.008 0.014 0.204 0.355 - d 1.230 1.280 31.24 32.51 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n24 249 rev. 0 12/93
15 all intersil products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporations quality certi?ations can be viewed at website www .intersil.com/quality/iso .asp. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or specifications at a ny time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to b e accurate and reliable. how- ever, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties wh ich may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil ltd. 8f-2, 96, sec. 1, chien-kuo north, taipei, taiwan 104 republic of china tel: 886-2-2515-8508 fax: 886-2-2515-8369 HI5812 small outline plastic packages (soic) notes: 1. symbols are defined in the ?o series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ??does not include interlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ??is the length of terminal for soldering to a substrate. 7. ??is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?? as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m24.3 (jedec ms-013-ad issue c) 24 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.020 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.5985 0.6141 15.20 15.60 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n24 247 0 o 8 o 0 o 8 o - rev. 0 12/93

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